HD6432351 datasheet(246/1025 Pages) RENESAS

246 / 1025 page

Section 7 DMA Controller (DMAC)

Rev. 3.00 Sep 15, 2006 page 212 of 988

REJ09B0330-0300

Bits 7 to 4—Data Transfer Enable (DTE): When DTE = 0, data transfer is disabled and the

activation source selected by the data transfer factor setting is ignored. If the activation source is

an internal interrupt, an interrupt request is issued to the CPU or DTC. If the DTIE bit is set to 1

when DTE = 0, the DMAC regards this as indicating the end of a transfer, and issues a transfer

end interrupt request to the CPU or DTC.

The conditions for the DTE bit being cleared to 0 are as follows:

• When initialization is performed

• When the specified number of transfers have been completed in a transfer mode other than

repeat mode

• When 0 is written to the DTE bit to forcibly abort the transfer, or for a similar reason

When DTE = 1, data transfer is enabled and the DMAC waits for a request by the activation

source selected by the data transfer factor setting. When a request is issued by the activation

source, DMA transfer is executed.

The condition for the DTE bit being set to 1 is as follows:

• When 1 is written to the DTE bit after the DTE bit is read as 0

Bit 7—Data Transfer Enable 1B (DTE1B): Enables or disables data transfer on channel 1B.

Bit 7

DTE1B

Description

Data transfer disabled

(Initial value)

Data transfer enabled

Bit 6—Data Transfer Enable 1A (DTE1A): Enables or disables data transfer on channel 1A.

Bit 6

DTE1A

Description

Data transfer disabled

(Initial value)

Data transfer enabled

HD6432351 Datasheet(PDF) 246 Page - Renesas Technology Corp