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HD6432351 Datasheet(PDF) 242 Page - Renesas Technology Corp |
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HD6432351 Datasheet(HTML) 242 Page - Renesas Technology Corp |
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242 / 1025 page ![]() Section 7 DMA Controller (DMAC) Rev. 3.00 Sep 15, 2006 page 208 of 988 REJ09B0330-0300 Channel B: Bit 3 DTF3 Bit 2 DTF2 Bit 1 DTF1 Bit 0 DTF0 Description 0 0 0 0 — (Initial value) 1 Activated by A/D converter conversion end interrupt 1 0 Activated by DREQ pin falling edge input* 1 Activated by DREQ pin low-level input 1 0 0 Activated by SCI channel 0 transmission complete interrupt 1 Activated by SCI channel 0 reception complete interrupt 1 0 Activated by SCI channel 1 transmission complete interrupt 1 Activated by SCI channel 1 reception complete interrupt 1 0 0 0 Activated by TPU channel 0 compare match/input capture A interrupt 1 Activated by TPU channel 1 compare match/input capture A interrupt 1 0 Activated by TPU channel 2 compare match/input capture A interrupt 1 Activated by TPU channel 3 compare match/input capture A interrupt 1 0 0 Activated by TPU channel 4 compare match/input capture A interrupt 1 Activated by TPU channel 5 compare match/input capture A interrupt 1 0 — 1 — Note: * Detected as a low level in the first transfer after transfer is enabled. The same factor can be selected for more than one channel. In this case, activation starts with the highest-priority channel according to the relative channel priorities. For relative channel priorities, see section 7.5.13, DMAC Multi-Channel Operation. |
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