HD6432351 datasheet(244/1025 Pages) RENESAS

244 / 1025 page

Section 7 DMA Controller (DMAC)

Rev. 3.00 Sep 15, 2006 page 210 of 988

REJ09B0330-0300

Bit 13—Single Address Enable 1 (SAE1): Specifies whether channel 1B is to be used for

transfer in dual address mode or single address mode.

Bit 13

SAE1

Description

Transfer in dual address mode

(Initial value)

Transfer in single address mode

This bit is invalid in full address mode.

Bit 12—Single Address Enable 0 (SAE0): Specifies whether channel 0B is to be used for

transfer in dual address mode or single address mode.

Bit 12

SAE0

Description

Transfer in dual address mode

(Initial value)

Transfer in single address mode

This bit is invalid in full address mode.

Bits 11 to 8—Data Transfer Acknowledge (DTA): These bits enable or disable clearing, when

DMA transfer is performed, of the internal interrupt source selected by the data transfer factor

setting.

When DTE = 1 and DTA = 1, the internal interrupt source selected by the data transfer factor

setting is cleared automatically by DMA transfer. When DTE = 1 and DTA = 1, the internal

interrupt source selected by the data transfer factor setting does not issue an interrupt request to the

CPU or DTC.

When DTE = 1 and DTA = 0, the internal interrupt source selected by the data transfer factor

setting is not cleared when a transfer is performed, and can issue an interrupt request to the CPU

or DTC in parallel. In this case, the interrupt source should be cleared by the CPU or DTC

transfer.

When DTE = 0, the internal interrupt source selected by the data transfer factor setting issues an

interrupt request to the CPU or DTC regardless of the DTA bit setting.

HD6432351 Datasheet(PDF) 244 Page - Renesas Technology Corp