HD6432351 datasheet(240/1025 Pages) RENESAS

240 / 1025 page

Section 7 DMA Controller (DMAC)

Rev. 3.00 Sep 15, 2006 page 206 of 988

REJ09B0330-0300

Bit 5—Repeat Enable (RPE): Used in combination with the DTIE bit in DMABCR to select the

mode (sequential, idle, or repeat) in which transfer is to be performed.

Bit 5

RPE

DMABCR

DTIE

Description

Transfer in sequential mode (no transfer end interrupt)

(Initial value)

Transfer in sequential mode (with transfer end interrupt)

Transfer in repeat mode (no transfer end interrupt)

Transfer in idle mode (with transfer end interrupt)

For details of operation in sequential, idle, and repeat mode, see section 7.5.2, Sequential Mode,

section 7.5.3, Idle Mode, and section 7.5.4, Repeat Mode.

Bit 4—Data Transfer Direction (DTDIR): Used in combination with the SAE bit in DMABCR

to specify the data transfer direction (source or destination). The function of this bit is therefore

different in dual address mode and single address mode.

DMABCR

SAE

Bit 4

DTDIR

Description

Transfer with MAR as source address and IOAR as destination

address

(Initial value)

Transfer with IOAR as source address and MAR as destination address

Transfer with MAR as source address and

DACK pin as write strobe

Transfer with

DACK pin as read strobe and MAR as destination address

HD6432351 Datasheet(PDF) 240 Page - Renesas Technology Corp