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HD6432351 Datasheet(PDF) 252 Page - Renesas Technology Corp |
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HD6432351 Datasheet(HTML) 252 Page - Renesas Technology Corp |
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252 / 1025 page ![]() Section 7 DMA Controller (DMAC) Rev. 3.00 Sep 15, 2006 page 218 of 988 REJ09B0330-0300 7.3.4 DMA Control Register (DMACR) DMACR is a 16-bit readable/writable register that controls the operation of each DMAC channel. In full address mode, DMACRA and DMACRB have different functions. DMACR is initialized to H'0000 by a reset, and in standby mode. DMACRA: 15 DTSZ 0 R/W 14 SAID 0 R/W 13 SAIDE 0 R/W 12 BLKDIR 0 R/W 11 BLKE 0 R/W 8 — 0 R/W 10 — 0 R/W 9 — 0 R/W Bit DMACRA Initial value R/W : : : : DMACRB: 7 — 0 R/W 6 DAID 0 R/W 5 DAIDE 0 R/W 4 — 0 R/W 3 DTF3 0 R/W 0 DTF0 0 R/W 2 DTF2 0 R/W 1 DTF1 0 R/W Bit DMACRB Initial value R/W : : : : Bit 15—Data Transfer Size (DTSZ): Selects the size of data to be transferred at one time. Bit 15 DTSZ Description 0 Byte-size transfer (Initial value) 1 Word-size transfer Bit 14—Source Address Increment/Decrement (SAID) |
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