HD6432351 datasheet(254/1025 Pages) RENESAS

254 / 1025 page

Section 7 DMA Controller (DMAC)

Rev. 3.00 Sep 15, 2006 page 220 of 988

REJ09B0330-0300

Bit 6—Destination Address Increment/Decrement (DAID)

Bit 5—Destination Address Increment/Decrement Enable (DAIDE): These bits specify

whether destination address register MARB is to be incremented, decremented, or left unchanged,

when data transfer is performed.

Bit 6

DAID

Bit 5

DAIDE

Description

MARB is fixed

(Initial value)

MARB is incremented after a data transfer

• When DTSZ = 0, MARB is incremented by 1 after a transfer

• When DTSZ = 1, MARB is incremented by 2 after a transfer

MARB is fixed

MARB is decremented after a data transfer

• When DTSZ = 0, MARB is decremented by 1 after a transfer

• When DTSZ = 1, MARB is decremented by 2 after a transfer

Bit 4—Reserved: Can be read or written to.

Bits 3 to 0—Data Transfer Factor (DTF3 to DTF0): These bits select the data transfer factor

(activation source). The factors that can be specified differ between normal mode and block

transfer mode.

• Normal Mode

Bit 3

DTF3

Bit 2

DTF2

Bit 1

DTF1

Bit 0

DTF0

Description

—

(Initial value)

—

Activated by

DREQ pin falling edge input

Activated by

DREQ pin low-level input

—

Auto-request (cycle steal)

Auto-request (burst)

—

*: Don’t care

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