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HD6432351 Datasheet(PDF) 307 Page - Renesas Technology Corp |
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HD6432351 Datasheet(HTML) 307 Page - Renesas Technology Corp |
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307 / 1025 page  Section 7 DMA Controller (DMAC) Rev. 3.00 Sep 15, 2006 page 273 of 988 REJ09B0330-0300 Figure 7.28 shows a transfer example in which TEND output is enabled and word-size single address mode transfer (read) is performed from external 8-bit, 2-state access space to an external device. DMA read φ Address bus DMA read DMA read DMA dead RD TEND DACK Bus release Bus release Bus release Bus release Last transfer cycle Figure 7.28 Example of Single Address Mode (Word Read) Transfer A one-byte or one-word transfer is performed for one transfer request, and after the transfer the bus is released. While the bus is released, one or more bus cycles are inserted by the CPU or DTC. In the transfer end cycle (the cycle in which the transfer counter reaches 0), a one-state DMA dead cycle is inserted after the DMA write cycle. |
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