HD6432351 datasheet(305/1025 Pages) RENESAS

305 / 1025 page

Section 7 DMA Controller (DMAC)

Rev. 3.00 Sep 15, 2006 page 271 of 988

REJ09B0330-0300

Figure 7.26 shows an example of

DREQ level activated block transfer mode transfer.

[1]

[2] [5]

[3] [6]

[4] [7]

Note: In write data buffer mode, bus breaks from [2] to [7] may be hidden, and not visible.

Acceptance after transfer enabling; the

DREQ pin low level is sampled on the rising

edge of

φ, and the request is held.

The request is cleared at the next bus break, and activation is started in the DMAC.

The DMA cycle is started.

Acceptance is resumed after the dead cycle is completed.

(As in [1], the

DREQ pin low level is sampled on the rising edge of φ, and the request is held.)

DMA

read

DMA

write

Address bus

DREQ

Idle

Write

Bus release

DMA control

Channel

Write

Transfer

source

Request

[1]

[3]

[2]

[4]

[6]

[5]

[7]

Acceptance resumes

DMA

dead

Bus

release

DMA

read

DMA

write

DMA

dead

Bus

release

1 block transfer

Idle

Dead

1 block transfer

Acceptance resumes

Request

Minimum of 2 cycles

Transfer

destination

Transfer

source

Transfer

destination

Minimum of 2 cycles

Read

Request clear period

Read

Request clear period

Idle

Figure 7.26 Example of

DREQ

DREQ Level Activated Block Transfer Mode Transfer

DREQ pin sampling is performed every cycle, with the rising edge of the next φ cycle after the

end of the DMABCR write cycle for setting the transfer enabled state as the starting point.

When the

DREQ pin low level is sampled while acceptance by means of the DREQ pin is

possible, the request is held in the DMAC. Then, when activation is initiated in the DMAC, the

request is cleared. After the end of the dead cycle, acceptance resumes,

DREQ pin low level

sampling is performed again, and this operation is repeated until the transfer ends.

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