HD6432351 datasheet(314/1025 Pages) RENESAS

314 / 1025 page

Section 7 DMA Controller (DMAC)

Rev. 3.00 Sep 15, 2006 page 280 of 988

REJ09B0330-0300

If transfer requests are issued simultaneously for more than one channel, or if a transfer request for

another channel is issued during a transfer, when the bus is released the DMAC selects the

highest-priority channel from among those issuing a request according to the priority order shown

in table 7.13.

During burst transfer, or when one block is being transferred in block transfer, the channel will not

be changed until the end of the transfer.

Figure 7.35 shows a transfer example in which transfer requests are issued simultaneously for

channels 0A, 0B, and 1.

DMA read

DMA write

DMA read

DMA write

DMA read

DMA write

DMA

read

Address bus

HWR

LWR

DMA control

Channel 0A

Channel 0B

Channel 1

Idle

Write

Idle

Read

Write

Idle

Read

Write

Read

Request clear

Request

hold

Request

hold

Request clear

Bus

release

Channel 0A

transfer

Bus

release

Channel 0B

transfer

Channel 1 transfer

Bus

release

Request

hold

Read

Selection

Non-

selection

Selection

Figure 7.35 Example of Multi-Channel Transfer

7.5.14

Relation between External Bus Requests, Refresh Cycles, the DTC, and the DMAC

There can be no break between a DMA cycle read and a DMA cycle write. This means that a

refresh cycle, external bus release cycle, or DTC cycle is not generated between the external read

and external write in a DMA cycle.

In the case of successive read and write cycles, such as in burst transfer or block transfer, a refresh

or external bus released state may be inserted after a write cycle. Since the DTC has a lower

priority than the DMAC, the DTC does not operate until the DMAC releases the bus.

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