HD6432351 datasheet(315/1025 Pages) RENESAS

315 / 1025 page

Section 7 DMA Controller (DMAC)

Rev. 3.00 Sep 15, 2006 page 281 of 988

REJ09B0330-0300

When DMA cycle reads or writes are accesses to on-chip memory or internal I/O registers, these

DMA cycles can be executed at the same time as refresh cycles or external bus release. However,

simultaneous operation may not be possible when a write buffer is used.

7.5.15

NMI Interrupts and DMAC

When an NMI interrupt is requested, burst mode transfer in full address mode is interrupted. An

NMI interrupt does not affect the operation of the DMAC in other modes.

In full address mode, transfer is enabled for a channel when both the DTE bit and the DTME bit

are set to 1. With burst mode setting, the DTME bit is cleared when an NMI interrupt is requested.

If the DTME bit is cleared during burst mode transfer, the DMAC discontinues transfer on

completion of the 1-byte or 1-word transfer in progress, then releases the bus, which passes to the

CPU.

The channel on which transfer was interrupted can be restarted by setting the DTME bit to 1 again.

Figure 7.36 shows the procedure for continuing transfer when it has been interrupted by an NMI

interrupt on a channel designated for burst mode transfer.

Resumption of

transfer on interrupted

channel

Set DTME bit to 1

Transfer continues

[1]

[2]

DTE = 1

DTME = 0

Transfer ends

Yes

[1]

[2]

Check that DTE = 1 and

DTME = 0 in DMABCRL

Write 1 to the DTME bit.

Figure 7.36 Example of Procedure for Continuing Transfer on Channel Interrupted by

NMI Interrupt

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