HD6432351 datasheet(318/1025 Pages) RENESAS

318 / 1025 page

Section 7 DMA Controller (DMAC)

Rev. 3.00 Sep 15, 2006 page 284 of 988

REJ09B0330-0300

7.6

Interrupts

The sources of interrupts generated by the DMAC are transfer end and transfer break. Table 7.13

shows the interrupt sources and their priority order.

Table 7.13 Interrupt Source Priority Order

Interrupt Source

Interrupt

Name

Short Address Mode

Full Address Mode

Interrupt

Priority Order

DEND0A

Interrupt due to end of

transfer on channel 0A

Interrupt due to end of

transfer on channel 0

High

DEND0B

Interrupt due to end of

transfer on channel 0B

Interrupt due to break in

transfer on channel 0

DEND1A

Interrupt due to end of

transfer on channel 1A

Interrupt due to end of

transfer on channel 1

DEND1B

Interrupt due to end of

transfer on channel 1B

Interrupt due to break in

transfer on channel 1

Low

Enabling or disabling of each interrupt source is set by means of the DTIE bit for the

corresponding channel in DMABCR, and interrupts from each source are sent to the interrupt

controller independently.

The relative priority of transfer end interrupts on each channel is decided by the interrupt

controller, as shown in table 7.13.

Figure 7.39 shows a block diagram of a transfer end/transfer break interrupt. An interrupt is

always generated when the DTIE bit is set to 1 while DTE bit is cleared to 0.

DTE/

DTME

DTIE

Transfer end/transfer

break interrupt

Figure 7.39 Block Diagram of Transfer End/Transfer Break Interrupt

In full address mode, a transfer break interrupt is generated when the DTME bit is cleared to o

while DTIEB bit is set to 1.

In both short address mode and full address mode, DMABCR should be set so as to prevent the

occurrence of a combination that constitutes a condition for interrupt generation during setting.

HD6432351 Datasheet(PDF) 318 Page - Renesas Technology Corp

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