HD6432351 datasheet(327/1025 Pages) RENESAS

327 / 1025 page

Section 8 Data Transfer Controller (DTC)

Rev. 3.00 Sep 15, 2006 page 293 of 988

REJ09B0330-0300

8.1.3

Table 8.1 summarizes the DTC registers.

Table 8.1

DTC Registers

Name

Abbreviation

R/W

Initial Value

Address*

DTC mode register A

MRA

—*

Undefined

—*

DTC mode register B

MRB

—*

Undefined

—*

DTC source address register

SAR

—*

Undefined

—*

DTC destination address register

DAR

—*

Undefined

—*

DTC transfer count register A

CRA

—*

Undefined

—*

DTC transfer count register B

CRB

—*

Undefined

—*

DTC enable registers

DTCER

R/W

H'00

H'FF30 to H'FF35

DTC vector register

DTVECR

R/W

H'00

H'FF37

Module stop control register

MSTPCR

R/W

H'3FFF

H'FF3C

Notes: 1. Lower 16 bits of the address.

2. Registers within the DTC cannot be read or written to directly.

3. Register information is located in on-chip RAM addresses H'F800 to H'FBFF. It cannot

be located in external space. When the DTC is used, do not clear the RAME bit in

SYSCR to 0.

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