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HD6432148SW Datasheet(PDF) 36 Page - Renesas Technology Corp |
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HD6432148SW Datasheet(HTML) 36 Page - Renesas Technology Corp |
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36 / 1177 page  Rev. 4.00 Sep 27, 2006 page xxxvi of xliv 17.1.1 Features................................................................................................................ 559 17.1.2 Block Diagram ..................................................................................................... 561 17.1.3 Input/Output Pins ................................................................................................. 562 17.1.4 Register Configuration......................................................................................... 562 17.2 Register Descriptions ........................................................................................................ 563 17.2.1 Keyboard Control Register H (KBCRH) ............................................................. 563 17.2.2 Keyboard Control Register L (KBCRL) .............................................................. 565 17.2.3 Keyboard Data Buffer Register (KBBR) ............................................................. 567 17.2.4 Module Stop Control Register (MSTPCR) .......................................................... 567 17.3 Operation .......................................................................................................................... 568 17.3.1 Receive Operation................................................................................................ 568 17.3.2 Transmit Operation .............................................................................................. 570 17.3.3 Receive Abort ...................................................................................................... 573 17.3.4 KCLKI and KDI Read Timing............................................................................. 576 17.3.5 KCLKO and KDO Write Timing......................................................................... 577 17.3.6 KBF Setting Timing and KCLK Control ............................................................. 578 17.3.7 Receive Timing.................................................................................................... 579 17.3.8 KCLK Fall Interrupt Operation............................................................................ 580 17.3.9 Usage Note........................................................................................................... 581 Section 18 Host Interface .................................................................................................. 583 18.1 Overview........................................................................................................................... 583 18.1.1 Features................................................................................................................ 583 18.1.2 Block Diagram ..................................................................................................... 584 18.1.3 Input and Output Pins .......................................................................................... 585 18.1.4 Register Configuration......................................................................................... 586 18.2 Register Descriptions ........................................................................................................ 587 18.2.1 System Control Register (SYSCR) ...................................................................... 587 18.2.2 System Control Register 2 (SYSCR2) ................................................................. 588 18.2.3 Host Interface Control Register (HICR) .............................................................. 590 18.2.4 Input Data Register 1 (IDR1)............................................................................... 592 18.2.5 Output Data Register 1 (ODR)............................................................................. 592 18.2.6 Status Register (STR) .......................................................................................... 593 18.2.7 Module Stop Control Register (MSTPCR) .......................................................... 595 18.3 Operation .......................................................................................................................... 595 18.3.1 Host Interface Activation ..................................................................................... 595 18.3.2 Control States....................................................................................................... 597 18.3.3 A20 Gate .............................................................................................................. 597 18.3.4 Host Interface Pin Shutdown Function ................................................................ 599 18.4 Interrupts ........................................................................................................................... 601 18.4.1 IBF1, IBF2, IBF3, IBF4....................................................................................... 601 |
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