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HD6432148SW Datasheet(PDF) 17 Page - Renesas Technology Corp |
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HD6432148SW Datasheet(HTML) 17 Page - Renesas Technology Corp |
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17 / 1177 page  Rev. 4.00 Sep 27, 2006 page xvii of xliv Item Page Revision (See Manual for Details) 23.10.7 Status Read Mode Figure 23.22 Status Read Mode Timing Waveforms 727 Figure 23.22 amended CE OE WE tces tnxtc tnxtc tdf tces tdh twep twep tdh toe tce tnxtc tf tr tf tr tceh tds tds tceh 24.7 Subclock Input Circuit 740 Note on Subclock Usage Description added 25.12 Usage Notes 764 Section 25.12 added 799 Table 26.15 amended Item Symbol Min Typ Max Unit Test Condition Reprogramming count N WEC 100* 8 10000* 9 — Times Data retention time* 10 t DRP 10 — — Years Programming Wait time after SWE-bit setting* 1 x10 —— µs 26.2.6 Flash Memory Characteristics Table 26.15 Flash Memory Characteristics (Programming/erasing operating range) 800 Notes 8 to 10 added Notes: 8. Minimum number of times for which all characteristics are guaranteed after rewriting (Guarantee range is 1 to minimum value). 9. Reference value for 25°C (as a guideline, rewriting should normally function up to this value). 10. Data retention characteristic when rewriting is performed within the specification range, including the minimum value. 26.3.3 AC Characteristics Table 26.20 Clock Timing 819 Table 26.20 amended Condition A Condition B Condition C 20 MHz 16 MHz 10 MHz Item Symbol Min Max Min Max Min Max Unit Test Conditions Oscillation settling time at reset (crystal) t OSC1 10 — 10 — 20 — ms Figure 26.6 Oscillation settling time in software standby (crystal) t OSC2 8 — 8 — 8 — ms Figure 26.7 Table 26.25 I 2C Bus Timing 829 Table 26.25 amended Ratings Item Symbol Min Typ Max Unit Test Conditions Notes SCL, SDA input fall time t Sf —— 300 ns Figure 26.28 SCL, SDA output fall time t of 20 + 0.1 Cb — 250 ns SCL, SDA input spike pulse elimination time t SP —— 1t cyc |
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