HD6432142 datasheet(360/1177 Pages) RENESAS

360 / 1177 page

Section 11 16-Bit Free-Running Timer

Rev. 4.00 Sep 27, 2006 page 316 of 1130

REJ09B0327-0400

Bit 2—Output Compare Interrupt B Enable (OCIBE): Selects whether to request output

compare interrupt B (OCIB) when output compare flag B (OCFB) in TCSR is set to 1.

Bit 2

OCIBE

Description

Output compare interrupt request B (OCIB) is disabled

(Initial value)

Output compare interrupt request B (OCIB) is enabled

Bit 1—Timer Overflow Interrupt Enable (OVIE): Selects whether to request a free-running

timer overflow interrupt (FOVI) when the timer overflow flag (OVF) in TCSR is set to 1.

Bit 1

OVIE

Description

Timer overflow interrupt request (FOVI) is disabled

(Initial value)

Timer overflow interrupt request (FOVI) is enabled

Bit 0—Reserved: This bit cannot be modified and is always read as 1.

11.2.7

Timer Control/Status Register (TCSR)

Bit

Initial value

Read/Write

ICFA

R/(W)*

ICFB

R/(W)*

ICFC

ICFD

OCFA

CCLRA

R/W

OCFB

R/(W)*

OVF

R/(W)*

Note: * Only 0 can be written in bits 7 to 1 to clear these flags.

TCSR is an 8-bit register used for counter clear selection and control of interrupt request signals.

TCSR is initialized to H'00 by a reset and in hardware standby mode.

Timing is described in section 11.3, Operation.

Bit 7—Input Capture Flag A (ICFA): This status flag indicates that the FRC value has been

transferred to ICRA by means of an input capture signal. When BUFEA = 1, ICFA indicates that

the old ICRA value has been moved into ICRC and the new FRC value has been transferred to

ICRA.

ICFA must be cleared by software. It is set by hardware, however, and cannot be set by software.

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