HD6432142 datasheet(31/1177 Pages) RENESAS

31 / 1177 page

Rev. 4.00 Sep 27, 2006 page xxxi of xliv

9.2.1

PWM Register Select (PWSL)............................................................................. 282

9.2.2

PWM Data Registers (PWDR0 to PWDR15) ...................................................... 284

9.2.3

PWM Data Polarity Registers A and B (PWDPRA and PWDPRB).................... 284

9.2.4

PWM Output Enable Registers A and B (PWOERA and PWOERB) ................. 285

9.2.5

Peripheral Clock Select Register (PCSR) ............................................................ 286

9.2.6

Port 1 Data Direction Register (P1DDR)............................................................. 286

9.2.7

Port 2 Data Direction Register (P2DDR)............................................................. 287

9.2.8

Port 1 Data Register (P1DR)................................................................................ 287

9.2.9

Port 2 Data Register (P2DR)................................................................................ 287

9.2.10 Module Stop Control Register (MSTPCR) .......................................................... 288

9.3

Operation .......................................................................................................................... 289

9.3.1

Correspondence between PWM Data Register Contents

and Output Waveform.......................................................................................... 289

Section 10 14-Bit PWM Timer (PWMX)..................................................................... 291

10.1

Overview........................................................................................................................... 291

10.1.1 Features................................................................................................................ 291

10.1.2 Block Diagram ..................................................................................................... 292

10.1.3 Pin Configuration................................................................................................. 293

10.1.4 Register Configuration......................................................................................... 293

10.2

Register Descriptions ........................................................................................................ 294

10.2.1 PWM (D/A) Counter (DACNT) .......................................................................... 294

10.2.2 D/A Data Registers A and B (DADRA and DADRB)......................................... 295

10.2.3 PWM D/A Control Register (DACR) .................................................................. 296

10.2.4 Module Stop Control Register (MSTPCR) .......................................................... 298

10.3

Bus Master Interface ......................................................................................................... 299

10.4

Operation .......................................................................................................................... 302

Section 11 16-Bit Free-Running Timer......................................................................... 307

11.1

Overview........................................................................................................................... 307

11.1.1 Features................................................................................................................ 307

11.1.2 Block Diagram ..................................................................................................... 308

11.1.3 Input and Output Pins .......................................................................................... 309

11.1.4 Register Configuration......................................................................................... 310

11.2

Register Descriptions ........................................................................................................ 311

11.2.1 Free-Running Counter (FRC) .............................................................................. 311

11.2.2 Output Compare Registers A and B (OCRA, OCRB) ......................................... 311

11.2.3 Input Capture Registers A to D (ICRA to ICRD) ................................................ 312

11.2.4 Output Compare Registers AR and AF (OCRAR, OCRAF) ............................... 313

11.2.5 Output Compare Register DM (OCRDM) ........................................................... 314

11.2.6 Timer Interrupt Enable Register (TIER) .............................................................. 314

HD6432142 Datasheet(PDF) 31 Page - Renesas Technology Corp

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