HD6432142 datasheet(96/1177 Pages) RENESAS

96 / 1177 page

Section 2 CPU

Rev. 4.00 Sep 27, 2006 page 52 of 1130

REJ09B0327-0400

2.6

Instruction Set

2.6.1

Overview

The H8S/2000 CPU has 65 types of instructions. The instructions are classified by function in

table 2.1.

Table 2.1

Instruction Classification

Function

Instructions

Size

Types

Data transfer

MOV

BWL

POP*

1, PUSH*1

LDM*

5, STM*5

MOVFPE*

3, MOVTPE*3

ADD, SUB, CMP, NEG

BWL

Arithmetic

operations

ADDX, SUBX, DAA, DAS

INC, DEC

BWL

ADDS, SUBS

MULXU, DIVXU, MULXS, DIVXS

EXTU, EXTS

TAS*

Logic operations

AND, OR, XOR, NOT

BWL

Shift

SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR

BWL

Bit-manipulation

BSET, BCLR, BNOT, BTST, BLD, BILD, BST, BIST, BAND,

BIAND, BOR, BIOR, BXOR, BIXOR

B14

Branch

Bcc*

2, JMP, BSR, JSR, RTS

—

System control

TRAPA, RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, NOP —

Block data transfer EEPMOV

—

Total: 65 types

Legend:

Byte

W: Word

Longword

Notes: 1. POP.W Rn and PUSH.W Rn are identical to MOV.W @SP+, Rn and MOV.W Rn,

@-SP.

POP.L ERn and PUSH.L ERn are identical to MOV.L @SP+, ERn and MOV.L ERn,

@-SP.

2. Bcc is the general name for conditional branch instructions.

3. Cannot be used in this LSI.

4. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction.

5. Only registers ER0 to ER6 should be used when using the STM/LDM instruction.

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