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HD6432142 Datasheet(PDF) 381 Page - Renesas Technology Corp |
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HD6432142 Datasheet(HTML) 381 Page - Renesas Technology Corp |
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381 / 1177 page ![]() Section 11 16-Bit Free-Running Timer Rev. 4.00 Sep 27, 2006 page 337 of 1130 REJ09B0327-0400 If automatic addition of OCRAR/OCRAF to OCRA is selected, and a compare-match occurs in the cycle following the OCRA, OCRAR and OCRAF write cycle, the OCRA, OCRAR and OCRAF write takes priority and the compare-match signal is inhibited. Consequently, the result of the automatic addition is not written to OCRA. Figure 11.21 shows this type of contention. T1 T2 OCRA or OCRB write cycle Address Internal write signal φ FRC OCR N M Write data OCR address N N + 1 Compare-match signal Inhibited Figure 11.20 Contention between OCR Write and Compare-Match (When Automatic Addition Function Is Not Used) |
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