HD6432142 datasheet(458/1177 Pages) RENESAS

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Section 14 Watchdog Timer (WDT)

Rev. 4.00 Sep 27, 2006 page 414 of 1130

REJ09B0327-0400

• WDT1 input clock selection

Bit 4

Bit 2

Bit 1

Bit 0

Description

PSS

CKS2

CKS1

CKS0

Clock

Overflow Period* (when

φφφφ = 20 MHz

and

φφφφ

SUB = 32.768 kHz)

φ/2 (Initial value) 25.6 µs

φ/64

819.2 µs

φ/128

1.6 ms

φ/512

6.6 ms

φ/2048

26.2 ms

φ/8192

104.9 ms

φ/32768

419.4 ms

φ/131072

1.68 s

φSUB/2

15.6 ms

φSUB/4

31.3 ms

φSUB/8

62.5 ms

φSUB/16

125 ms

φSUB/32

250 ms

φSUB/64

500 ms

φSUB/128

1 s

φSUB/256

2 s

Note:

The overflow period is the time from when TCNT starts counting up from H'00 until

overflow occurs.

14.2.3

System Control Register (SYSCR)

CS2E

R/W

IOSE

R/W

INTM1

INTM0

R/W

XRST

RAME

R/W

NMIEG

R/W

HIE

R/W

Bit

Initial value

Read/Write

Only bit 3 is described here. For details on functions not related to the watchdog timer, see

sections 3.2.2 and 5.2.1, System Control Register (SYSCR), and the descriptions of the relevant

modules.

Bit 3—External Reset (XRST): Indicates the reset source. When the watchdog timer is used, a

reset can be generated by watchdog timer overflow in addition to external reset input. XRST is a

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