HD6432142 datasheet(477/1177 Pages) RENESAS

477 / 1177 page

Section 15 Serial Communication Interface (SCI, IrDA)

Rev. 4.00 Sep 27, 2006 page 433 of 1130

REJ09B0327-0400

Bit 1

Bit 0

CKS1

CKS0

Description

φ clock

(Initial value)

φ/4 clock

φ/16 clock

φ/64 clock

15.2.6

Serial Control Register (SCR)

TIE

R/W

RIE

R/W

MPIE

R/W

CKE0

R/W

TEIE

R/W

CKE1

R/W

Bit

Initial value

Read/Write

SCR is a register that performs enabling or disabling of SCI transfer operations, serial clock output

in asynchronous mode, and interrupt requests, and selection of the serial clock source.

SCR can be read or written to by the CPU at all times.

SCR is initialized to H'00 by a reset, and in standby mode, watch mode, subactive mode, subsleep

mode, and module stop mode.

Bit 7—Transmit Interrupt Enable (TIE): Enables or disables transmit-data-empty interrupt

(TXI) request generation when serial transmit data is transferred from TDR to TSR and the TDRE

flag in SSR is set to 1.

Bit 7

TIE

Description

Transmit-data-empty interrupt (TXI) request disabled*

(Initial value)

Transmit-data-empty interrupt (TXI) request enabled

Note:

TXI interrupt request cancellation can be performed by reading 1 from the TDRE flag,

then clearing it to 0, or clearing the TIE bit to 0.

HD6432142 Datasheet(PDF) 477 Page - Renesas Technology Corp

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