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HD6432142 Datasheet(PDF) 603 Page - Renesas Technology Corp |
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HD6432142 Datasheet(HTML) 603 Page - Renesas Technology Corp |
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603 / 1177 page ![]() Section 17 Keyboard Buffer Controller Rev. 4.00 Sep 27, 2006 page 559 of 1130 REJ09B0327-0400 Section 17 Keyboard Buffer Controller Provided in the H8S/2148 Group and H8S/2147N; not provided in the H8S/2144 Group. 17.1 Overview The H8S/2148 Group and H8S/2147N have three on-chip keyboard buffer controller channels, designated 0, 1, and 2. The keyboard buffer controller is provided with functions conforming to the PS/2 interface specifications. Data transfer using the keyboard buffer controller employs a data line (KD) and a clock line, providing economical use of connectors, board surface area, etc. Figure 17.1 shows how the keyboard buffer controller is connected. 17.1.1 Features • Conforms to PS/2 interface specifications • Direct bus drive (via the KCLK and KD pins) • Interrupt sources: on completion of data reception and on detection of clock edge • Error detection: parity error and stop bit monitoring |
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