HD6432142 datasheet(251/1177 Pages) RENESAS

251 / 1177 page

Section 7 Data Transfer Controller (DTC)

Rev. 4.00 Sep 27, 2006 page 207 of 1130

REJ09B0327-0400

7.4

Interrupts

An interrupt request is issued to the CPU when the DTC finishes the specified number of data

transfers, or a data transfer for which the DISEL bit was set to 1. In the case of interrupt activation,

the interrupt set as the activation source is generated. These interrupts to the CPU are subject to

CPU mask level and interrupt controller priority level control.

In the case of activation by software, a software-activated data transfer end interrupt (SWDTEND)

is generated.

When the DISEL bit is 1 and one data transfer has ended, or the specified number of transfers

have ended, after data transfer ends, the SWDTE bit is held at 1 and an SWDTEND interrupt is

generated. The interrupt handling routine should clear the SWDTE bit to 0.

When the DTC is activated by software, an SWDTEND interrupt is not generated during a data

transfer wait or during data transfer even if the SWDTE bit is set to 1.

7.5

Usage Notes

Module Stop

When the MSTP14 bit in MSTPCR is set to 1, the DTC clock stops, and the DTC enters the

module stop state. However, 1 cannot be written in the MSTP14 bit while the DTC is operating.

When the DTC is placed in the module stop state, the DTCER registers must all be in the cleared

state when the MSTP14 bit is set to 1.

On-Chip RAM

The MRA, MRB, SAR, DAR, CRA, and CRB registers are all located in on-chip RAM. When the

DTC is used, the RAME bit in SYSCR must not be cleared to 0.

DTCE Bit Setting

For DTCE bit setting, read/write operations must be performed using bit-manipulation instructions

such as BSET and BCLR. For the initial setting only, however, when multiple activation sources

are set at one time, it is possible to disable interrupts and write after executing a dummy read on

the relevant register.

HD6432142 Datasheet(PDF) 251 Page - Renesas Technology Corp