HD6432142 datasheet(317/1177 Pages) RENESAS

317 / 1177 page

Section 8 I/O Ports

Rev. 4.00 Sep 27, 2006 page 273 of 1130

REJ09B0327-0400

8.12.2

Table 8.25 summarizes the port B registers.

Table 8.25

Port B Registers

Name

Abbreviation

R/W

Initial Value

Address*

Port B data direction register

PBDDR

H'00

H'FFBE*

Port B output data register

PBODR

R/W

H'00

H'FFBC

Port B input data register

PBPIN

Undefined

H'FFBD*

Notes: 1. Lower 16 bits of the address.

2. PBDDR has the same address as P7PIN.

3. PBPIN has the same address as P8DDR.

Port B Data Direction Register (PBDDR)

Bit

765

432

PB7DDR PB6DDR PB5DDR PB4DDR PB3DDR PB2DDR PB1DDR PB0DDR

Initial value

000

Read/Write

PBDDR is an 8-bit write-only register, the individual bits of which specify input or output for the

pins of port B. PBDDR has the same address as P7PIN, and if read, the port 7 pin states will be

returned.

Setting a PBDDR bit to 1 makes the corresponding port B pin an output pin, while clearing the bit

to 0 makes the pin an input pin.

PBDDR is initialized to H'00 by a reset and in hardware standby mode. It retains its prior state in

software standby mode.

• Modes 1, 2 and 3 (EXPE = 1)

When the ABW bit in WSCR is cleared to 0, port B pins automatically become data I/O pins

(D7 to D0), regardless of the input/output direction indicated by PBDDR. When the ABW bit

is 1, a port B pin becomes an output port if the corresponding PBDDR bit is set to 1, and an

input port if the bit is cleared to 0.

Data I/O pins go to the high-impedance state after a reset, and in hardware standby mode or

software standby mode.

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