R5F21183SP datasheet(49/257 Pages) RENESAS

49 / 257 page

R8C/18 Group, R8C/19 Group

6. Programmable I/O Ports

Rev.1.30

Apr 14, 2006

Page 34 of 233

REJ09B0222-0130

Figure 6.7

Registers PUR0 and PUR1

Figure 6.8

DRR Register

Pull-Up Control Register 0

Symbol

Address

After Reset

PUR0

00FCh

00XX0000b

Bit Symbol

Bit Name

Function

NOTE:

P1_0 to P1_3 pull-up(1)

Reserved bits

P3_4 to P3_5, and P3_7 pll-up(1)

—

P3_3 pull-up(1)

0 : Not pulled up

1 : Pulled up

Nothing is assigned. If necessary, set to 0.

When read, the content is undefined.

0 : Not pulled up

1 : Pulled up

Set to 0.

b7 b6 b5 b4

PU03

b3 b2 b1

(b1-b0)

When this bit is set to 1 (pulled up), the pin w hose direction bit is set to 0 (input mode) is pulled up.

PU07

PU06

P1_4 to P1_7 pull-up(1)

PU02

—

(b5-b4)

Pull-Up Control Register 1

Symbol

Address

Af ter Reset

PUR1

00FDh

XXXXXX0Xb

Bit Symbol

Bit Name

Function

NOTE:

—

When the PU11 bit is set to 1 (pulled up), and the PD4_5 bit is set to 0 (input mode), the P4_5 pin is pulled up.

b3 b2 b1

b7 b6 b5 b4

—

(b7-b2)

Nothing is assigned. If necessary, set to 0.

When read, the content is 0.

—

(b0)

Nothing is assigned. If necessary, set to 0.

When read, the content is undef ined.

—

PU11

P4_5 pull-up(1)

0 : Not pulled up

1 : Pulled up

Port P1 Drive Capacity Control Register

Symbol

Address

After Reset

DRR

00FEh

00h

Bit Symbol

Bit Name

Function

DRR0

DRR2

Set to 0.

b7 b6 b5 b4

000 0

b3 b2 b1 b0

P1_2 drive capacity

DRR1

P1_1 drive capacity

Set P1 N-channel output transistor drive

capacity.

0 : Low

1 : High

Reserved bits

(b7-b4)

P1_0 drive capacity

DRR3

P1_3 drive capacity

R5F21183SP Datasheet(PDF) 49 Page - Renesas Technology Corp

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