HD6433636SW datasheet(283/418 Pages) RENESAS

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10.3.8

Application Notes

When using SCI3, attention should be paid to the following matters.

Relation between Bit TDRE and Writing Data to TDR: Bit TDRE in the serial status register

(SSR) is a status flag indicating that TDR does not contain new transmit data. TDRE is

automatically cleared to 0 when data is written to TDR. When SCI3 transfers data from TDR to

TSR, bit TDRE is set to 1.

Data can be written to TDR regardless of the status of bit TDRE. However, if new data is written

to TDR while TDRE is cleared to 0, assuming the data held in TDR has not yet been shifted to

TSR, it will be lost. For this reason, it is recommended for securing serial data transmission that

writing transmit data to TDR should be performed only once (not two or more times), always after

confirming that bit TDRE is set to 1.

Operation when Multiple Receive Errors Occur at the Same Time: When two or more receive

errors occur at the same time, the status flags in SSR are set as shown in table 10.17. If an overrun

error occurs, data is not transferred from RSR to RDR, and receive data is lost.

Table 10.17

SSR Status Flag States and Transfer of Receive Data

SSR Status Flags

Receive Data Transfer

RDRF* OER

FER

PER

(RSR

→ RDR)

Receive Error Status

Overrun error

Framing error

Parity error

Overrun error + framing error

Overrun error + parity error

Framing error + parity error

Overrun error + framing error + parity error

: Receive data transferred from RSR to RDR

× : Receive data not transferred from RSR to RDR

Note: * RDRF keeps the same state as before the data was received.

HD6433636SW Datasheet(PDF) 283 Page - Renesas Technology Corp