HD6433636SW datasheet(286/418 Pages) RENESAS

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Relationship between Bit RDRF and Reading RDR: While SCI3 is receiving, it checks the

RDRF flag. If the RDRF flag is cleared to 0 when the reception of one frame of data is completed,

data reception ends normally. If RDRF is set to 1, an overrun error occurs.

RDRF is automatically cleared to 0 when the contents of RDR are read. If RDR is read more than

once, the second and later reads will be performed with RDRF cleared to 0. Note that when RDR

is read while RDRF is 0, data from the next frame may be read if this reading operation is carried

out at the same time that the reception of the next frame is completed. This is illustrated in figure

10.25.

Communica-

tion line

RDRF

RDR

Frame 1

Frame 2

Frame 3

Data 1

Data 2

Data 3

Data 1

Data 2

RDR read

At (A), data 1 is read.

At (B), data 2 is read.

(A)

(B)

Figure 10.25 Relationship between Data and RDR Read Timing

To avoid the situation described above, RDR reading should be carried out only once (not two or

more times) after confirming that bit RDRF is set to 1.

When reading RDR more than once, be sure to copy any data read for the first time to RAM, for

example, and use the copied data. Also note that RDR reading should be carried out with a safe

margin just before reception of the next frame is completed. More concretely, RDR reading should

be completed before transferring bit 7 in the synchronous mode or before transferring the stop bit

in the asynchronous mode

HD6433636SW Datasheet(PDF) 286 Page - Renesas Technology Corp