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HD6433636SW Datasheet(PDF) 285 Page - Renesas Technology Corp |
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HD6433636SW Datasheet(HTML) 285 Page - Renesas Technology Corp |
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285 / 418 page  271 16 clock cycles 8 clock cycles Start bit Internal base clock Receive data (RXD) Synchronization sampling timing Data sampling timing 07 15 7 15 0 D0 D1 0 Figure 10.24 Receive Data Sampling Timing in Asynchronous Mode The receive margin in asynchronous mode can therefore be derived from the following equation. M = (0.5 – ) – – (L – 0.5) F × 100% 1 2N D – 0.5 N ...................... Equation (1) M: Receive margin (%) N: Ratio of clock frequency to bit rate (N = 16) D: Clock duty cycle (D = 0.5 to 1) L: Frame length (L = 9 to 12) F: Absolute value of clock frequency error In equation (1), if F (absolute value of clock frequency error) = 0 and D (clock duty cycle) = 0.5, the receive margin is 46.875% as given by equation (2) below. When D = 0.5 and F = 0, M = {0.5 – 1/(2 × 16)} × 100% = 46.875% ...................................... Equation (2) This value is theoretical. In actual system designs a margin of from 20 to 30 percent should be allowed. |
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