HD6433636SW datasheet(301/418 Pages) RENESAS

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Bit 7—Clock Select (CKS): Bits CKS and CKS1 select the A/D conversion speed.

Conversion Time

Bit 5: CKS1

Bit 7: CKS

Conversion Period

ø = 2 MHz

ø = 5 MHz

Reserved (initial value)

—

124/ø

µs

24.8

µs

62/ø

µs

12.4

µs

31/ø

15.5

µs—*

Note: * Operation is not guaranteed if the conversion time is less than 12.4

µs. Set the bits to get a

value of at least 12.4

µs.

Bit 6—External Trigger Select (TRGE): Bit 6 enables or disables the start of A/D conversion by

external trigger input.

Bit 6: TRGE

Description

Disables start of A/D conversion by external trigger

(initial value)

Enables start of A/D conversion by rising or falling edge of external trigger at

ADTRG*

Note: * The external trigger (

ADTRG) edge is selected by bit IEG4 of the interrupt edge select

Bit 5—Clock Select 1 (CKS1): Bits CKS and CKS1 select the A/D conversion speed. See bit 7,

clock select (CKS) for details.

Bit 4—Reserved Bit: Bit 4 is reserved; it is always read as 1, and cannot be modified.

Bits 3 to 0—Channel Select 3 to 0 (CH3 to CH0): Bits 3 to 0 select the analog input channel.

The channel selection should be made while bit ADSF is cleared to 0.

Bit 3:

CH3

Bit 2:

CH2

Bit 1:

CH1

Bit 0:

CH0

Analog Input Channel

No channel selected

(initial value)

Reserved

1000AN

1AN

10AN

1AN

Reserved

Note: * Don’t care

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