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M16C/1N Datasheet(PDF) 71 Page - Renesas Technology Corp |
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M16C/1N Datasheet(HTML) 71 Page - Renesas Technology Corp |
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71 / 238 page  Rev.1.00 Oct 20, 2004 page 59 of 222 M16C/1N Group 10. Interrupt REJ09B0007-0100Z INT1 INT3 TCIN Timer Z Timer X CAN0 error INT2 INT0 Timer C CNTR0 Timer Y CAN0 wake up UART1 reception UART0 reception A/D conversion CAN0 successful reception Timer 1 UART1 transmission UART0 transmission Key input CAN0 successful transmission Processor interrupt priority level (IPL) Interrupt enable flag (I flag) Address match Oscillation stop detection/Watchdog timer DBC (Note 1) High Low Level 0 (initial value) Priority level of each interrupt Interrupt request accepted UART0 receive hardware interrupt enable bit Note 1: Interrupts used for debugging purposes only. Priority of peripheral I/O interrupts (if priority levels are same) Interrupt request level judgment output signal UART0 reception (Note 1) Reset Figure 10.9 Interrupt resolution circuit |
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