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SH7052 Datasheet(PDF) 102 Page - Renesas Technology Corp |
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SH7052 Datasheet(HTML) 102 Page - Renesas Technology Corp |
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102 / 919 page  76 6.1.2 Block Diagram Figure 6.1 is a block diagram of the INTC. CPU SR Interrupt request Com- parator CPU/ DMAC request judg- ment Priority ranking judg- ment Input control (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) ISR ICR IPR IPRA, IPRC to IPRL Module bus Bus interface I3 I2 I1 I0 INTC IRQOUT NMI IRQ0 IRQ1 IRQ2 IRQ3 UBC DMAC ATU-II CMT A/D SCI WDT HCAN UBC: DMAC: ATU-II: CMT: A/D: SCI: User break controller Direct memory access controller Advanced timer unit Compare match timer A/D converter Serial communication interface WDT: HCAN: ICR: ISR: IPRA, IPRC to IPRL: SR: Watchdog timer Hitachi controller area network Interrupt control register IRQ status register Interrupt priority level setting registers A, C to L Status register Figure 6.1 INTC Block Diagram |
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