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SH7052 Datasheet(PDF) 103 Page - Renesas Technology Corp |
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SH7052 Datasheet(HTML) 103 Page - Renesas Technology Corp |
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103 / 919 page ![]() 77 6.1.3 Pin Configuration Table 6.1 shows the INTC pin configuration. Table 6.1 Pin Configuration Name Abbreviation I/O Function Non-maskable interrupt input pin NMI I Input of non-maskable interrupt request signal Interrupt request input pins IRQ0 to IRQ3 I Input of maskable interrupt request signals 6.1.4 Register Configuration The INTC has the 14 registers shown in table 6.2. These registers set the priority of the interrupts and control external interrupt input signal detection. Table 6.2 Register Configuration Name Abbr. R/W Initial Value Address Access Sizes Interrupt priority register A IPRA R/W H'0000 H'FFFF ED00 8, 16, 32 Interrupt priority register C IPRC R/W H'0000 H'FFFF ED04 8, 16, 32 Interrupt priority register D IPRD R/W H'0000 H'FFFF ED06 8, 16, 32 Interrupt priority register E IPRE R/W H'0000 H'FFFF ED08 8, 16, 32 Interrupt priority register F IPRF R/W H'0000 H'FFFF ED0A 8, 16, 32 Interrupt priority register G IPRG R/W H'0000 H'FFFF ED0C 8, 16, 32 Interrupt priority register H IPRH R/W H'0000 H'FFFF ED0E 8, 16, 32 Interrupt priority register I IPRI R/W H'0000 H'FFFF ED10 8, 16, 32 Interrupt priority register J IPRJ R/W H'0000 H'FFFF ED12 8, 16, 32 Interrupt priority register K IPRK R/W H'0000 H'FFFF ED14 8, 16, 32 Interrupt priority register L IPRL R/W H'0000 H'FFFF ED16 8, 16, 32 Interrupt control register ICR R/W *1 H'FFFF ED18 8, 16, 32 IRQ status register ISR R(W)* 2 H'0000 H'FFFF ED1A 8, 16, 32 Notes: Three access cycles are required for byte access and word access, and six cycles for longword access. 1. The value when the NMI pin is high is H'8000; when the NMI pin is low, it is H'0000. 2. Only 0 can be written, in order to clear flags. |
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