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SH7052 Datasheet(PDF) 170 Page - Renesas Technology Corp |
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SH7052 Datasheet(HTML) 170 Page - Renesas Technology Corp |
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170 / 919 page  144 9.2.3 DMA Transfer Count Registers 0 to 3 (DMATCR0 to DMATCR3) DMA transfer count registers 0 to 3 (DMATCR0 to DMATCR3) are 24-bit read/write registers that specify the transfer count for the channel (byte count, word count, or longword count) in bits 23 to 0. Specifying H'000001 gives a transfer count of 1, while H'000000 gives the maximum setting, 16,777,216 transfers. During DMAC operation, these registers indicate the remaining number of transfers. The upper 8 bits of DMATCR always read 0. The write value, also, should always be 0. The value after a power-on reset and in standby mode is undefined. Bit: 31 30 29 28 27 26 25 24 —— —— ——— — Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R Bit: 23 22 21 20 19 18 17 16 Initial value: — — — — — — — — R/W: R/W R/W R/W R/W R/W R/W R/W R/W Bit: 15 14 13 12 11 10 9 8 Initial value: — — — — — — — — R/W: R/W R/W R/W R/W R/W R/W R/W R/W Bit: 7 6 5 4 3 2 1 0 Initial value: — — — — — — — — R/W: R/W R/W R/W R/W R/W R/W R/W R/W |
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