 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
SH7052 Datasheet(PDF) 169 Page - Renesas Technology Corp |
|
|
|||||||||||||||||||||||||||||
SH7052 Datasheet(HTML) 169 Page - Renesas Technology Corp |
|
|
169 / 919 page  143 Bit: 31 30 29 28 27 26 25 24 Initial value: — — — — — — — — R/W: R/W R/W R/W R/W R/W R/W R/W R/W Bit: 23 22 21 … … 2 1 0 …… Initial value: — — — … … — — — R/W: R/W R/W R/W … … R/W R/W R/W 9.2.2 DMA Destination Address Registers 0 to 3 (DAR0 to DAR3) DMA destination address registers 0 to 3 (DAR0 to DAR3) are 32-bit readable/writable registers that specify the destination address of a DMA transfer. These registers have a count function, and during a DMA transfer, they indicate the next destination address. Specify a 16-bit boundary when performing 16-bit data transfers, and a 32-bit boundary when performing 32-bit data transfers. Operation cannot be guaranteed if any other addresses are set. The value after a power-on reset and in standby mode is undefined. Bit: 31 30 29 28 27 26 25 24 Initial value: — — — — — — — — R/W: R/W R/W R/W R/W R/W R/W R/W R/W Bit: 23 22 21 … … 2 1 0 …… Initial value: — — — … … — — — R/W: R/W R/W R/W … … R/W R/W R/W |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
