SH7052 datasheet(167/919 Pages) RENESAS

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141

9.1.3

Table 9.1 summarizes the DMAC registers. The DMAC has a total of 17 registers. Each channel

has four registers, and one overall DMAC control register is shared by all channels.

Table 9.1

DMAC Registers

Channel Name

Abbr.

R/W

Initial

Value

Address

Size

Access

Size

DMA source

address register 0

SAR0

R/W

Undefined

H'FFFFECC0 32 bits

16, 32*

DMA destination

address register 0

DAR0

R/W

Undefined

H'FFFFECC4 32 bits

16, 32*

DMA transfer

count register 0

DMATCR0 R/W

Undefined

H'FFFFECC8 32 bits

16, 32*

DMA channel

control register 0

CHCR0

R/W*

H'00000000 H'FFFFECCC 32 bits

16, 32*

DMA source

address register 1

SAR1

R/W

Undefined

H'FFFFECD0 32 bits

16, 32*

DMA destination

address register 1

DAR1

R/W

Undefined

H'FFFFECD4 32 bits

16, 32*

DMA transfer

count register 1

DMATCR1 R/W

Undefined

H'FFFFECD8 32 bits

16, 32*

DMA channel

control register 1

CHCR1

R/W*

H'00000000 H'FFFFECDC 32 bits

16, 32*

DMA source

address register 2

SAR2

R/W

Undefined

H'FFFFECE0 32 bits

16, 32*

DMA destination

address register 2

DAR2

R/W

Undefined

H'FFFFECE4 32 bits

16, 32*

DMA transfer

count register 2

DMATCR2 R/W

Undefined

H'FFFFECE8 32 bits

16, 32*

DMA channel

control register 2

CHCR2

R/W*

H'00000000 H'FFFFECEC 32 bits

16, 32*

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