SH7052 datasheet(175/919 Pages) RENESAS

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• Bit 3—Transfer Mode (TM): Specifies the bus mode for data transfer.

Bit 3: TM

Description

Cycle-steal mode

(Initial value)

Burst mode

• Bit 2—Interrupt Enable (IE): When this bit is set to 1, interrupt requests are generated after the

number of data transfers specified in DMATCR (when TE = 1).

Bit 2: IE

Description

Interrupt request not generated on completion of DMATCR-specified

number of transfers

(Initial value)

Interrupt request enabled on completion of DMATCR-specified number

of transfers

• Bit 1—Transfer End (TE): This bit is set to 1 after the number of data transfers specified by

DMATCR. At this time, if the IE bit is set to 1, an interrupt request is generated.

If data transfer ends before TE is set to 1 (for example, due to an NMI or address error, or

clearing of the DE bit or DME bit of DMAOR) TE is not set to 1. With this bit set to 1, data

transfer is disabled even if the DE bit is set to 1.

Bit 1: TE

Description

DMATCR-specified number of transfers not completed

(Initial value)

[Clearing condition]

0 write after TE = 1 read, power-on reset, standby mode

DMATCR-specified number of transfers completed

• Bit 0—DMAC Enable (DE): DE enables operation in the corresponding channel.

Bit 0: DE

Description

Operation of the corresponding channel disabled

(Initial value)

Operation of the corresponding channel enabled

Transfer is initiated if this bit is set to 1 when auto-request is specified (RS4 to RS0 settings). With

an on-chip module request, when a transfer request occurs after this bit is set to 1, transfer is

initiated. If this bit is cleared during a data transfer, transfer is suspended.

If the DE bit has been set, but TE = 1, then if the DME bit of DMAOR is 0, and the NMIF or AE

bit of DMAOR is 1, the transfer enable state is not entered.

SH7052 Datasheet(PDF) 175 Page - Renesas Technology Corp