SH7052 datasheet(178/919 Pages) RENESAS

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9.3

Operation

When there is a DMA transfer request, the DMAC starts the transfer according to the channel

priority order; when the transfer end conditions are satisfied, it ends the transfer. Transfers can be

requested in two modes: auto-request and on-chip peripheral module request. Transfer is

performed only in dual address mode, and either direct or indirect address transfer mode can be

used. The bus mode can be either burst or cycle-steal.

9.3.1

DMA Transfer Flow

After the DMA source address registers (SAR), DMA destination address registers (DAR), DMA

transfer count register (DMATCR), DMA channel control registers (CHCR), and DMA operation

to the following procedure:

1. The DMAC checks to see if transfer is enabled (DE = 1, DME = 1, TE = 0, NMIF = 0,

AE = 0).

2. When a transfer request comes and transfer has been enabled, the DMAC transfers 1 transfer

unit of data (determined by the TS0 and TS1 setting). For an auto-request, the transfer begins

automatically when the DE bit and DME bit are set to 1. The DMATCR value will be

decremented by 1 upon each transfer. The actual transfer flows vary by address mode and bus

mode.

3. When the specified number of transfers have been completed (when DMATCR reaches 0), the

transfer ends normally. If the IE bit of CHCR is set to 1 at this time, a DEI interrupt is sent to

the CPU.

4. When an address error occurs in the DMAC or an NMI interrupt is generated, the transfer is

aborted. Transfer is also aborted when the DE bit of CHCR or the DME bit of DMAOR is

cleared to 0.

SH7052 Datasheet(PDF) 178 Page - Renesas Technology Corp