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SH7052 Datasheet(PDF) 181 Page - Renesas Technology Corp

Part # SH7052
Description  SuperHTM RISC engine
PDF  919 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7052 Datasheet(HTML) 181 Page - Renesas Technology Corp

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155
Table 9.2
Selecting On-Chip Peripheral Module Request Modes with the RS Bits
RS4
RS3
RS2
RS1
RS0
DMAC
Transfer
Request
Source
DMAC Transfer
Request Signal
Transfer
Source
Transfer
Destination
Bus Mode
00001
SCI0
transmit
block
TXI0 (SCI0 transmit-
data-empty transfer
request)
Don’t care*
TDR0
Burst/cycle-
steal
1
0
SCI0
receive
block
RXI0 (SCI0 receive-
data-full transfer
request)
RDR0
Don’t care*
Burst/cycle-
steal
1
SCI1
transmit
block
TXI1 (SCI1 transmit-
data-empty transfer
request)
Don’t care*
TDR1
Burst/cycle-
steal
1
0
0
SCI1
receive
block
RXI1 (SCI1 receive-
data-full transfer
request)
RDR1
Don’t care*
Burst/cycle-
steal
1
SCI2
transmit
block
TXI2 (SCI2 transmit-
data-empty transfer
request)
Don’t care*
TDR2
Burst/cycle-
steal
1
0
SCI2
receive
block
RXI2 (SCI2 receive-
data-full transfer
request)
RDR2
Don’t care*
Burst/cycle-
steal
1
SCI3
transmit
block
TXI3 (SCI3 transmit-
data-empty transfer
request)
Don’t care*
TDR3
Burst/cycle-
steal
1000
SCI3
receive
block
RXI3 (SCI3 receive-
data-full transfer
request)
RDR3
Don’t care*
Burst/cycle-
steal
1
SCI4
transmit
block
TXI4 (SCI4 transmit-
data-empty transfer
request)
Don’t care*
TDR4
Burst/cycle-
steal
1
0
SCI4
receive
block
RXI4 (SCI4 receive-
data-full transfer
request)
RDR4
Don’t care*
Burst/cycle-
steal
1
A/D0
ADI0 (A/D0
conversion end
interrupt)
ADDR0 to
ADDR11
Don’t care*
Burst/cycle-
steal
1
0
0
A/D1
ADI1 (A/D1
conversion end
interrupt)
ADDR12 to
ADDR23
Don’t care*
Burst/cycle-
steal
1
Reserved
1
1
HCAN
RM0 (HCAN
receive interrupt)
MD0 to
MD15
Don’t care*
Burst/cycle-
steal



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