SH7052 datasheet(185/919 Pages) RENESAS

185 / 919 page

159

Transfer destination

address

Transfer source

address

A21 to A0

CSn

D15 to D0

WRH,

WRL

Figure 9.4 Direct Address Transfer Timing in Dual Address Mode

Indirect Address Transfer Mode: In this mode the memory address storing the data actually to

be transferred is specified in the DMAC internal transfer source address register (SAR3).

Therefore, in indirect address transfer mode, the DMAC internal transfer source address register

value is read first. This value is first stored in the DMAC. Next, the read value is output as the

address, and the value stored at that address is again stored in the DMAC. Finally, the subsequent

read value is written to the address specified by the transfer destination address register, ending

one cycle of DMAC transfer.

In indirect address mode (figure 9.5), the transfer destination, transfer source, and indirect address

storage destination are all 16-bit external memory locations, and transfer in this example is

conducted in 16-bit or 8-bit units. Timing for this transfer example is shown in figure 9.6.

In indirect address mode, one NOP cycle (figure 9.6) is required until the data read as the indirect

address is output to the address bus. When transfer data is 32-bit, the third and fourth bus cycles

each need to be doubled, giving a required total of six bus cycles and one NOP cycle for the whole

operation.

SH7052 Datasheet(PDF) 185 Page - Renesas Technology Corp