SH7052 datasheet(183/919 Pages) RENESAS

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ADDR12 to ADDR23:

A/D1 data registers

MD0 to MD15:

HCAN message data

Note: * External memory, memory-mapped external device, on-chip memory, on-chip peripheral

module (excluding DMAC, BSC, and UBC)

9.3.3

Channel Priority

When the DMAC receives simultaneous transfer requests on two or more channels, it selects a

channel according to the following priority order:

• CH0 > CH1 > CH2 > CH3

9.3.4

DMA Transfer Types

The DMAC supports the transfers shown in table 9.3. It operates in dual address mode, in which

both the transfer source and destination addresses are output. The dual address mode consists of a

direct address mode, in which the output address value is the object of a direct data transfer, and

an indirect address mode, in which the output address value is not the object of the data transfer,

but the value stored at the output address becomes the transfer object address. The actual transfer

operation timing varies with the bus mode. The DMAC has two bus modes: cycle-steal mode and

burst mode.

Table 9.3

Supported DMA Transfers

Transfer Destination

Transfer Source

External

Memory

Memory-Mapped

External Device

On-Chip

Memory

On-Chip

Peripheral Module

External memory

Supported

Memory-mapped

external device

Supported

On-chip memory

Supported

On-chip peripheral

module

Supported

9.3.5

Dual Address Mode

Dual address mode is used for access of both the transfer source and destination by address.

Transfer source and destination can be accessed either internally or externally. Dual address mode

is subdivided into two other modes: direct address transfer mode and indirect address transfer

mode.

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