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SH7052 Datasheet(PDF) 187 Page - Renesas Technology Corp |
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SH7052 Datasheet(HTML) 187 Page - Renesas Technology Corp |
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187 / 919 page  161 CK A21 to A0 D15 to D0 CSn WRH, WRL RD Data read cycle Data write cycle (1st) (2nd) Internal address bus Internal data bus DMAC indirect address buffer DMAC data buffer Transfer source address (H) Transfer source address (L) NOP Indirect address Transfer destina- tion address Transfer data NOP Transfer data Indirect address Transfer data (4th) (3rd) NOP cycle *2 Indirect address (H) Indirect address (L) Transfer data Transfer source address*1 Indirect address Transfer data Indirect address Address read cycle Notes: 1. The internal address bus is controlled by the port and does not change. 2. The DMAC does not latch the value until 32-bit data is read from the internal data bus. External memory space → External memory space (External memory space has 16-bit width) Figure 9.6 Dual Address Mode and Indirect Address Transfer Timing Example 1 |
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