SH7052 datasheet(188/919 Pages) RENESAS

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Figure 9.7 shows an example of timing in indirect address mode when transfer source and indirect

address storage locations are in internal memory, the transfer destination is an on-chip peripheral

module with 2-cycle access space, and transfer data is 8-bit.

Since the indirect address storage destination and the transfer source are in internal memory, these

can be accessed in one cycle. The transfer destination is 2-cycle access space, so two data write

cycles are required. One NOP cycle is required until the data read as the indirect address is output

to the address bus.

Internal

address

bus

Internal

data

bus

DMAC

indirect

address

buffer

DMAC

data

buffer

Internal memory space

→ Internal memory space

Transfer

source

address

NOP

Indirect

address

Transfer

destination

address

Indirect

address

Indirect

address

Transfer

data

Transfer data

Address

read cycle

NOP

cycle

Data

read cycle

Data write cycle (4th)

(1st)

(2nd)

(3rd)

Figure 9.7 Dual Address Mode and Indirect Address Transfer Timing Example 2

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