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SH7052 Datasheet(PDF) 176 Page - Renesas Technology Corp

Part # SH7052
Description  SuperHTM RISC engine
PDF  919 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7052 Datasheet(HTML) 176 Page - Renesas Technology Corp

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9.2.5
DMAC Operation Register (DMAOR)
DMAOR is a 16-bit readable/writable register that controls the overall operation of the DMAC.
Register values are initialized to 0 by a power-on reset and in standby mode.
Bit:
15
14
13
12
11
10
9
8
——
——
———
—
Initial value:
0
0
0
0
0
0
0
0
R/W:
R
R
R
R
R
R
R
R
Bit:
7
6
5
4
3
2
1
0
—
—
—
—
—
AE
NMIF
DME
Initial value:
0
0
0
0
0
0
0
0
R/W:
R
R
R
R
R
R/(W)*
R/(W)*
R/W
Note: * A 0 write only is valid after 1 is read at the AE and NMIF bits.
• Bits 15 to 3—Reserved: These bits are always read 0 and should always be written with 0.
• Bit 2—Address Error Flag (AE): Indicates that an address error has occurred during DMA
transfer. If this bit is set during a data transfer, transfers on all channels are suspended. The
CPU cannot write a 1 to the AE bit. Clearing is effected by a 0 write after a 1 read.
Bit 2: AE
Description
0
No address error, DMA transfer enabled
(Initial value)
[Clearing condition]
Write AE = 0 after reading AE = 1
1
Address error, DMA transfer disabled
[Setting condition]
Address error due to DMAC



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