SH7052 datasheet(193/919 Pages) RENESAS

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• When DMATCR is 0: When the DMATCR value becomes 0 and the corresponding channel's

DMA transfer ends, the transfer end flag bit (TE) is set in CHCR. If the IE (interrupt enable)

bit has been set, a DMAC interrupt (DEI) request is sent to the CPU.

• When DE of CHCR is 0: Software can halt a DMA transfer by clearing the DE bit in the

channel’s CHCR. The TE bit is not set when this happens.

Conditions for Ending on All Channels Simultaneously: Transfers on all channels end when

the NMIF (NMI flag) bit or AE (address error flag) bit is set to 1 in DMAOR, or when the DME

bit in DMAOR is cleared to 0.

• When the NMIF or AE bit is set to 1 in DMAOR: When an NMI interrupt or DMAC address

error occurs, the NMIF or AE bit is set to 1 in DMAOR and all channels stop their transfers.

The DMAC obtains the bus right, and if these flags are set to 1 during execution of a transfer,

DMAC halts operation when the transfer processing currently being executed ends, and

transfers the bus right to the other bus master. Consequently, even if the NMIF or AE bit is set

to 1 during a transfer, the DMA source address register (SAR), designation address register

(DAR), and transfer count register (DMATCR) are all updated. The TE bit is not set. To

resume the transfers after NMI interrupt or address error processing, the NMIF or AE flag

must be cleared. To avoid restarting a transfer on a particular channel, clear its DE bit to 0 in

CHCR.

When the processing of a one-unit transfer is complete: In a dual address mode direct address

transfer, even if an address error occurs or the NMI flag is set during read processing, the

transfer will not be halted until after completion of the following write processing. In such a

case, SAR, DAR, and DMATCR values are updated. In the same manner, the transfer is not

halted in indirect address transfers until after the final write processing has ended.

• When DME is cleared to 0 in DMAOR: Clearing the DME bit to 0 in DMAOR aborts the

transfers on all channels. The TE bit is not set.

9.3.11

DMAC Access from CPU

The space addressed by the DMAC is 3-cycle space. Therefore, when the CPU becomes the bus

master and accesses the DMAC, a minimum of three basic clock cycles are required for one bus

cycle. Also, since the DMAC is located in word space, while a word-size access to the DMAC is

completed in one bus cycle, a longword-size access is automatically divided into two word

accesses, requiring two bus cycles (six basic clock cycles). These two bus cycles are executed

consecutively; a different bus cycle is never inserted between the two word accesses. This applies

to both write accesses and read accesses.

SH7052 Datasheet(PDF) 193 Page - Renesas Technology Corp