SH7052 datasheet(195/919 Pages) RENESAS

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Table 9.6

Transfer Conditions and Register Set Values for Transfer between A/D

Converter and On-Chip Memory

Transfer Conditions

Value

Transfer source: on-chip A/D converter ch1 (A/D1)

SAR2

H'FFFFF820

Transfer destination: on-chip memory

DAR2

H'FFFF6000

Transfer count: 128 times (reload count 32 times)

DMATCR2

H'00000080

Transfer source address: incremented

CHCR2

H'010C110D

Transfer destination address: incremented

Transfer request source: A/D converter ch1 (A/D1)

Bus mode: burst

Transfer unit: byte

Interrupt request generation at end of transfer

DMAC master enable on

DMAOR

H'0001

When address reload is on, the SAR2 value returns to its initially set value every four transfers. In

the above example, when a transfer request is input from the A/D1, the byte-size data is first read

in from the H'FFFFF820 register of on-chip A/D1 and that data is written to internal address

H'FFFF6000. Because a byte-size transfer was performed, the SAR2 and DAR2 values at this

point are H'FFFFF821 and H'FFFF6001, respectively. Also, because this is a burst transfer, the

bus right remains secured, so continuous data transfer is possible.

When four transfers are completed, if address reload is off, execution continues with the fifth and

sixth transfers and the SAR2 value continues to increment from H'FFFFF824 to H'FFFFF825 to

H'FFFFF826 and so on. However, when address reload is on, DMAC transfer is halted upon

completion of the fourth transfer and the bus right request signal to the CPU is cleared. At this

time, the value stored in SAR2 is not H'FFFFF823

→ H'FFFFF824, but H'FFFFF823 →

H'FFFFF820, a return to the initially set address. The DAR2 value always continues to be

decremented regardless of whether address reload is on or off.

The DMAC internal status, due to the above operation after completion of the fourth transfer, is

indicated in table 9.7 for both address reload on and off.

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