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HD64F2144B Datasheet(PDF) 73 Page - Renesas Technology Corp |
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HD64F2144B Datasheet(HTML) 73 Page - Renesas Technology Corp |
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73 / 546 page  Section 2 CPU Rev. 1.00 Jun.24, 2005 Page 41 of 510 REJ09B0241-0100 Table 2.6 Shift Instructions Instruction Size* Function SHAL SHAR B/W/L Rd (shift) → Rd Performs an arithmetic shift on data in a general register. 1-bit or 2 bit shift is possible. SHLL SHLR B/W/L Rd (shift) → Rd Performs a logical shift on data in a general register. 1-bit or 2 bit shift is possible. ROTL ROTR B/W/L Rd (rotate) → Rd Rotates data in a general register. 1-bit or 2 bit rotation is possible. ROTXL ROTXR B/W/L Rd (rotate) → Rd Rotates data including the carry flag in a general register. 1-bit or 2 bit rotation is possible. Note: * Size refers to the operand size. B: Byte W: Word L: Longword |
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