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HD64F2144B Datasheet(PDF) 15 Page - Renesas Technology Corp |
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HD64F2144B Datasheet(HTML) 15 Page - Renesas Technology Corp |
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15 / 546 page ![]() Rev. 1.00 Jun.24, 2005 Page xv of xxxii 11.6.5 System Reset by RESO Signal (Available for H8S/2144B) ................................. 270 11.6.6 Counter Values during Transitions between High-Speed, Sub-Active, and Watch Modes ................................................................................................. 270 Section 12 Serial Communication Interface (SCI and IrDA) ..............................271 12.1 Features.............................................................................................................................. 271 12.2 Input/Output Pins ...............................................................................................................273 12.3 Register Descriptions ......................................................................................................... 273 12.3.1 Receive Shift Register (RSR) ............................................................................... 274 12.3.2 Receive Data Register (RDR) ............................................................................... 274 12.3.3 Transmit Data Register (TDR).............................................................................. 274 12.3.4 Transmit Shift Register (TSR) .............................................................................. 274 12.3.5 Serial Mode Register (SMR) ................................................................................ 275 12.3.6 Serial Control Register (SCR) .............................................................................. 277 12.3.7 Serial Status Register (SSR) ................................................................................. 279 12.3.8 Serial Interface Mode Register (SCMR)............................................................... 281 12.3.9 Bit Rate Register (BRR) ....................................................................................... 282 12.3.10 Keyboard Comparator Control Register (KBCOMP)........................................... 289 12.4 Operation in Asynchronous Mode ..................................................................................... 290 12.4.1 Data Transfer Format............................................................................................ 290 12.4.2 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode ............................................................................................. 292 12.4.3 Clock..................................................................................................................... 293 12.4.4 SCI Initialization (Asynchronous Mode) .............................................................. 294 12.4.5 Data Transmission (Asynchronous Mode)............................................................ 295 12.4.6 Serial Data Reception (Asynchronous Mode)....................................................... 297 12.5 Multiprocessor Communication Function.......................................................................... 301 12.5.1 Multiprocessor Serial Data Transmission ............................................................. 303 12.5.2 Multiprocessor Serial Data Reception .................................................................. 305 12.6 Operation in Clock Synchronous Mode ............................................................................. 308 12.6.1 Clock..................................................................................................................... 308 12.6.2 SCI Initialization (Clock Synchronous Mode)...................................................... 309 12.6.3 Serial Data Transmission (Clock Synchronous Mode) ......................................... 310 12.6.4 Serial Data Reception (Clock Synchronous Mode) .............................................. 313 12.6.5 Simultaneous Serial Data Transmission and Reception (Clock Synchronous Mode) .................................................................................. 316 12.7 IrDA Operation ..................................................................................................................318 12.8 Interrupt Sources................................................................................................................ 321 12.9 Usage Notes ....................................................................................................................... 322 12.9.1 Module Stop Mode Setting ................................................................................... 322 |
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