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LTC2301CDEXPBF Datasheet(PDF) 19 Page - Linear Technology

Part # LTC2301CDEXPBF
Description  1-/2-Channel, 12-Bit ADCs with I2C Compatible Interface
PDF  24 Pages
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Manufacturer  LINER [Linear Technology]
Direct Link  http://www.linear.com
Logo LINER - Linear Technology

LTC2301CDEXPBF Datasheet(HTML) 19 Page - Linear Technology

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LTC2301/LTC2305
19
23015f
APPLICATIONS INFORMATION
Continuous Read/Write
Once the conversion cycle is complete, the LTC2301/
LTC2305 can be written to and then read from using the
Repeated Start (Sr) command. Figure 9 shows a cycle which
begins with a data Write, a repeated Start, followed by a
Read and concluded with a Stop command. The following
conversion begins after all 16 bits are read out of the device
or after a Stop command. The following conversion will
be performed using the newly programmed data.
Synchronizing Multiple LTC2301/LTC2305s with a
Global Address Call
In applications where several LTC2301/LTC2305s or other
I2C SAR ADCs from Linear Technology Corporation are
used on the same I2C bus, all converters can be synchro-
nized through the use of a global address call. Prior to
issuing the global address call, all converters must have
completed a conversion cycle. The master then issues a
Start, followed by the global address 1110111, and a write
request. All converters will be selected and acknowledge
the request. The master then sends a write byte (optional)
followed by the Stop command. This will update the
channel selection (optional) and simultaneously initiate
a conversion for all ADCs on the bus (see Figure 10).
In order to synchronize multiple converters without chang-
ing the channel, a Stop command may be issued after
acknowledgement of the global write command. Global
read commands are not allowed and the converters will
NAK a global read request.
Nap Mode
The ADCs enter nap mode after a conversion is complete
(tCONV) if the SLP bit is set to a logic 0. The supply current
decreases to 225μA in nap mode between conversions,
thereby reducing the average power dissipation as the
sample rate decreases. For example, the LTC2301/LTC2305
draw an average of 300μA at a 1ksps sampling rate. The
LTC2301/LTC2305 keep only the reference (VREF) and
reference buffer (REFCOMP) circuitry active when in nap
mode.
Figure 9. Write, Read, Start Conversion
Figure 10. Synchronize Multiple LTC2301/LTC2305s with a Global Address Call
S
CONVERSION
NAP
DATA OUTPUT
CONVERSION
CONVERSION
DATA
OUTPUT
W
ACK
WRITE
7-BIT ADDRESS
Sr
R
ACK
23015 F09
READ
7-BIT ADDRESS
P
S
SDA
SCL
CONVERSION
NAP
LTC2301/LTC2305
DATA OUTPUT
CONVERSION OF ALL LTC2301/05s
W
ACK
WRITE (OPTIONAL)
GLOBAL ADDRESS
P
LTC2301/LTC2305
LTC2301/LTC2305
23015 F10



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