ADV3203ASWZ datasheet(5/20 Pages) AD

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ADV3202/ADV3203

Rev. 0 | Page 5 of 20

TIMING CHARACTERISTICS (SERIAL MODE)

Specifications subject to change without notice.

Table 3.

Limit

Parameter

Symbol

Min

Typ

Max

Unit

Serial Data Setup Time

CLK Pulse Width

Serial Data Hold Time

CLK Pulse Separation

150

CLK to UPDATE Delay

160

UPDATE Pulse Width

CLK to DATA OUT Valid

130

Propagation Delay, UPDATE to Switch On or Off

Data Load Time, CLK = 5 MHz, Serial Mode

38.6

μs

RESET Time

160

TRANSFER DATA FROM SERIAL

LATCHES DURING LOW LEVEL

OUT00 (D0)

OUT15 (D5)

CLAMP

ON/OFF

1 = LATCHED

0 = TRANSPARENT

DATA OUT

UPDATE

DATA IN

CLK

LOAD DATA INTO

SERIAL REGISTER

ON RISING EDGE

Figure 2. Timing Diagram, Serial Mode

Table 4. Logic Levels, DVCC = 3.3 V

VIH

VIL

VOH

VOL

IIH

IIL

IOH

IOL

RESET, CS,

CLK, DATA IN,

UPDATE, OSDS

RESET, CS,

CLK, DATA IN,

UPDATE, OSDS

DATA OUT

RESET, CS,

CLK, DATA IN,

UPDATE, OSDS

RESET, CS,

CLK, DATA IN,

UPDATE, OSDS

DATA OUT

2.5 V min

0.8 V max

2.7 V min

0.5 V max

0.5 μA typ

−0.5 μA typ

3 mA typ

−3 mA typ

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