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TMDS361 Datasheet(PDF) 12 Page - Texas Instruments |
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TMDS361 Datasheet(HTML) 12 Page - Texas Instruments |
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12 / 42 page ![]() TMDS DDC and Local I 2C Pins ELECTRICAL CHARACTERISTICS TMDS361 SLLS919 – DECEMBER 2008............................................................................................................................................................................................ www.ti.com DDC I2C Buffer or Repeater: The TMDS361 provides buffering on the DDC I2C interface for each of the input ports connected. This feature isolates the capacitance on the source side from the sink side and thus helps in passing system-level compliance. See the DDC I2C Function Description section for a detailed description on how the DDC I2C buffer operates. Note that a key requirement on the sink side is that the VIL(Sink) (input to TMDS361) should be less than 0.4 V. This requirement should be met for the DDC I2C buffer to function properly. There are three settings of VIL(Sink) and VOL(Sink) that can be chosen based on OVS settings (See Table 8 through Table 11). Local I2C Interface: The TMDS361 includes a slave I2C interface to control device features like TMDS input port selection, TMDS output edge-rate control, power management, DDC buffer OVS settings, etc. See Table 8 through Table 11. The TMDS361 is designed to be controlled via a local I2C interface or GPIO interface, based on the status of the I2C_SEL pin. The local I2C interface in the TMDS361 is only a slave I2C interface. See the I2C INTERFACE NOTES section for a detailed description of I2C functionality. over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IL Low-level input current VCC = 3.6 V, VI = 0 V –10 10 µA Ilkg(Sink) Input leakage current Sink pins VCC = 3.6 V, VI = 4.95 V –10 10 µA DC bias = 2.5 V, AC = 3.5 Vp-p, CIO(Sink) Input/output capacitance Sink pins 15 pF f = 100 kHz VIH(Sink) High-level input voltage Sink pins 2.1 5.5 V VIL1(Sink) Low-level input voltage Sink pins OVS 1 –0.2 0.4 V VOL1(Sink) Low-level output voltage Sink pins IO = 3 mA, OVS = HIGH 0.6 0.7 V VIL2(Sink) Low-level input voltage Sink pins OVS 2 –0.2 0.4 V VOL2(Sink) Low-level output voltage Sink pins IO = 3 mA, OVS = LOW 0.5 0.6 V VIL3(Sink) Low-level input voltage Sink pins OVS 3 –0.2 0.3 V VOL3(Sink) Low-level output voltage Sink pins IO = 3 mA, OVS = high-Z 0.4 0.5 V Ilkg(I2C) Input leakage current Port[1:3] pins VCC = 3.6 V, VI = 4.95 V –10 10 µA DC bias = 2.5 V, AC = 3.5 Vp-p, CIO(I2C) Input/output capacitance Port[1:3] pins 15 pF f = 100 kHz VIH(I2C) High-level input voltage Port[1:3] pins 2.1 5.5 V VIL(I2C) Low-level input voltage Port[1:3] pins –0.2 1.5 V VOL(I2C) Low-level output voltage Port[1:3] pins IO = 3 mA 0.2 V 12 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s) :TMDS361 |
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