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MPC8641D Datasheet(PDF) 88 Page - Freescale Semiconductor, Inc |
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MPC8641D Datasheet(HTML) 88 Page - Freescale Semiconductor, Inc |
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88 / 140 page  MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 1 88 Freescale Semiconductor Serial RapidIO Figure 55. Single Frequency Sinusoidal Jitter Limits 15.8 Receiver Eye Diagrams For each baud rate at which an LP-Serial receiver is specified to operate, the receiver shall meet the corresponding Bit Error Rate specification (Table 59, Table 60, Table 61) when the eye pattern of the receiver test signal (exclusive of sinusoidal jitter) falls entirely within the unshaded portion of the Receiver Input Compliance Mask shown in Figure 56 with the parameters specified in Table 62. The eye pattern of the receiver test signal is measured at the input pins of the receiving device with the device replaced with a 100 Ohm +/– 5% differential resistive load. 8.5 UI p-p 0.10 UI p-p Sinusoidal Jitter Amplitude 22.1 kHz 1.875 MHz 20 MHz Frequency |
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